6. Conclusions

Notice: This document has been provided by the contributing authors as a means to ensure timely dissemination of scholarity and technical work on a noncommercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons copying this information will adhere to the terms and constraints invoked by each author's copyright. These works may not be reposted without the explicit permission of the copyright holder. The two-dimensional FIR filter algorithms are measured for different kernel sizes. Input to the filter is a 1280 by 1024 pixel grayscale image using 8 bits per pixel. The algorithms have been implemented on the different machines, by optimizing the code manually (improving the use of local interconnect and loading of four input words concurrently). Further a larger application example namely the JPEG image compression algorithm is compared. A more detailed description of the MoM-3 implementation of this algorithm can be found in [HBK95]. Table 1 shows the computed performance values and the acceleration factor of the Xputer prototype by using the rDPA as computational element. A scalable, parallel and reconfigurable datapath architecture (rDPA) has been presented. The architecture provides higher flexibility, higher throughput and better area efficiency than FPGAs available commercially. The rDPA architecture can be used as reconfigurable ALU for Xputers as well as for rapid prototyping of high speed datapaths. A datapath synthesis system has been implemented which allows the mapping of statements onto the rDPA array without user interaction. For FIR filter and the JPEG compression algorithm, acceleration factors between 12 and 60 have been obtained compared to one of the fastest Sparc stations currently available. A second realisation of the rDPA using standard cells with a datapath compiler will soon be submitted for fabrication. It provides 32 bit datapaths and arithmetic resources for integer and fixed-point numbers. The datapath synthesis system is completely specified. The optimization, the placement, as well as the scheduling have been implemented. The code generation is currently being implemented.